Complex SOC.

-> In some complex SOCs testbench  also requires processing unit instance for controlling BFMs to every peripherals.

-> It seems to be a mirror image for some few peripherals.
     ex.    If SOC contains ETHERNET and for verification of  trasmission and receiving of it.
         -> SOC and TESTBENCH has different instance of an ethernet and ethernet of SOC will
              transmit the data and those data will transfered to receiver part of testbench ethernet
              and for that confugration for receiving of the ethernet at testbench requires processor
              of testbench side.
         -> testbench received data on ethernet that will stored in a temporary memory and that will
             be compared with whatever data transfer through SOC ethernet.   

how to read from peripheral through ARM?

step 1 for read operation on to the peripherals with using C testcase


          As per earlier post of confugration of peripheral we can define the complete address of register .
           #define    SPI_BASE_ADDR        0x3FFA0000
           #define    SPI_CONTROL_REG   ((unsigned volatile int *)(SPI_BASE_ADDR + 0x00000004)
step2
      And in main task of C testcase

    main()
   {
      unsigned int read_data;
      read_data   =  *SPI_CONTROL_REG;
   }
 
And finally from this testcase ARM will read the register value of SPI_CONTROL_REG.

How to configure peripherals through ARM?

-> In SOC every peripheral has its own indivisual base address that is defined by design team.
-> Suppose                                       peripheral           base address
                                                         SPI                    0x3FFA0000
                                                         I2C                    0x3EAB0000
                                                         WDT                 0x4ACD0000
-> And inside peripheral each register has indivisual address that is called offset address.
-> so If we want to configure control register of SPI,
     then check what is the offset address for control register into the specification of SPI document.
         Assume offset address for control register is 0x004 then complete address is
         full address = base address of SPI + offset address of control register .
                           = 0x3FFA0000          +  0x004
                           = 0x3FFA0004
-> for that we can write very simple code of C with using pointer.
STEPS

1)    first define the base address of peripheral and registers offset address.
       example :        #define    SPI_BASE_ADDR        0x3FFA0000
                             #define    SPI_CONTROL_REG   ((unsigned volatile int *)(SPI_BASE_ADDR + 0x00000004)

               And this statements should be outside of main program of c testcase.

2)    Now using pointer write data on that address which you want to update.
                             suppose data is 32 bit value 0xA00003FC
                             so write operation will happen with this command.
                             *SPI_CONTROL_REG   =  0xA00003FC  ;
        this command will write 0xA00003FC on to the spi control register.

              And this statements should be inside of main  program of c testcase.                                            

How to load C testcase inside in processing unit?

-> Assume processing unit is ARM processor.
-> We have to code first C testcase for our intented operation .
-> Then we have to convert that C code into hex file with using simple tool related commands.
-> SOC TOP file will helps to load that hex files in to ARM.
-> so for loading that hex code into ARM ROM we can use verilog construct "READMEMH".
-> In readmemh we have to give hex file name and path or hierarchy of ARM ROM so it will load whole hex file in to ARM ROM.
-> And whatever we have given instruction in to C code that all instruction will fatch by ARM.
-> ARM will responds according the instructions in to the SOC.

Which things SOC verification architecture will contains?

-> It will mainly combination of SOC RTL and testbenches which they are connected with using SOC TOP file.
-> In starting RTL and Testbench parts will be different but those things are connected into the SOC TOP files,so you will find interconnect between TB and RTL in TOP files. 

How system verilog helps to verify SOC?

-> After doing IP level verification we have complete env of verification of IP.
-> So in SOC processing unit(ex.ARM)  will become a master and it works as driver to the IP so we can remove those driver part from the env which we have used for confugration of IP.
-> Slave bfm can be there for driving data .
-> and passive part of verification env of IP we can plug in to SOC and it will monitors the IP responces and it will give display statement.

What basic things it requires for testing a SOC?

-> Basically verification of SOC is mainly intented for checking the integration of different IPs and processing units which they are connected with using BUS protocols.
-> So for checking the integration master has to initiate the transactions on bus for accessing the peripherals and configuring it,and for that C or assembly code should be executed by master (ex. ARM) .

what is SOC?

-> system on chip.

-> This figure shows the basic architecture for ARM based SOC (bus protocol AMBA it may differ for different SOC)
-> It is complex system which is containing of processing unit(ex. ARM ,ARC) and different IPs for practical applications.