-> After doing IP level verification we have complete env of verification of IP.
-> So in SOC processing unit(ex.ARM) will become a master and it works as driver to the IP so we can remove those driver part from the env which we have used for confugration of IP.
-> Slave bfm can be there for driving data .
-> and passive part of verification env of IP we can plug in to SOC and it will monitors the IP responces and it will give display statement.
-> So in SOC processing unit(ex.ARM) will become a master and it works as driver to the IP so we can remove those driver part from the env which we have used for confugration of IP.
-> Slave bfm can be there for driving data .
-> and passive part of verification env of IP we can plug in to SOC and it will monitors the IP responces and it will give display statement.
The main strength of the system verilog is the various types of assertions that it supports facilitating the designers to catch the 'performance bugs' or a 'synchronization bugs in a protocol' a lot faster with minimum efforts. Apart from that, SV is developed on OOPs backbone, hence facilitating portability and all the advantages of OOPs.
ReplyDeleteOf course most painful thing in using SV is to develop a frame work!!!! :P